Barrel muon track reconstruction with deep learning

Level-1 trigger data scouting in the CMS experiment

Fabio Cufino

CERN Summer Student - Openlab

Supervisors Rocco Ardino, Thomas James

August 13, 2024

CMS Detector

[CMS collaboration]

CMS Detector

Key Components

  • Silicon Tracker: Detects charged particles, reconstructs trajectories
  • Electromagnetic Calorimeter (ECAL): Measures energy of photons and electrons
  • Hadronic Calorimeter (HCAL): Measures energy of hadrons
  • Muon Detectors: Capture muon tracks
    • DTs, RPCs, CSCs, GEMs
[CMS collaboration]

Challenges

High collision rate

  • Collision Rate: 40 MHz \(\; \Longrightarrow \;\) 25 ns between bunch crossings
  • Select the potentially interesting events: Trigger

CMS Trigger System

2 Trigger System Stages

  • Purpose: Filters collision data from 40 MHz to ~1 kHz for storage.
Schematic representation of the Phase-1 trigger system
  1. Level-1 Trigger (L1T)
    • Hardware-based: Custom electronics
    • Focus: Fast decisions making
    • Data sources: Muon and Calo
    • Rate reduction: 40 MHz \(\rightarrow\) 100 kHz
  1. High-Level Trigger (HLT)
    • Software-based: Processor farm
    • Focus: Detailed analysis
    • Data sources: All subdetectors
    • Final rate: ~1 kHz

Challenges

High collision rate

  • Collision Rate: 40 MHz \(\; \Longrightarrow \;\) Trigger
  • Level-1 trigger discards ∼99.75% of events
  • Potentially interesting data has to be discarded: L1 scouting system

Data Scouting

At Level-1 trigger

L1 Data Scouting Strategy:

  • Idea: Use L1 trigger chain objects with reduced detail at various stages of the L1 trigger chain
  • Online processing using heterogeneous computing methods (FPGAs, GPUs)

Data Scouting

At Level-1 trigger

Schematic representation of the Level-1 trigger
[Nicolò Lai, CERN Summer School 2023 Report]

Demonstrator System set up for Run-3:

  • Data Sources: Global Trigger (GT), Global Muon Trigger (GMT), Calorimeter Trigger, Barrel Muon Track Finder (BMTF)
  • Hardware: FPGA-based processing boards via optical links

Data Scouting

TwinMux boards

Demonstrator System set up for Run-3:

  • Data Sources: Global Trigger (GT), Global Muon Trigger (GMT), Calorimeter Trigger, Barrel Muon Track Finder (BMTF)
  • Hardware: FPGA-based processing boards via optical links

TwinMux boards (60)

  • Objective: process trigger primitives from

    1. Drift Tubes
    2. Resistive Plate Chambers (RPCs)

  • Create the super-primitives (stubs)

  • Then processed by the BMTF for track reconstruction

Track Reconstruction

L1 Method

The BMTF utilizes a Kalman filter algorithm for the reconstruction tasks sice 2021

[Nicolò Lai, CERN Summer School 2023 Report]

New Approach

  • Refining muon track reconstruction in the barrel at Level-1 trigger using ML algorithms for FPGA
    • low latency requested

  • Goal: Outperform the Level-1 trigger Kalman filter.

  • How: \(3\) different NNs with 2, 3, 4 stubs as input (number of stubs per muon can vary)

Results

Results

2 stubs NN

  • Fully connected Neural Network
  • Architecture:
    • Input size: \(2\times 11\)
    • Hidden Layers: \(32,32,16,8\;\)
    • Output Size: \(3\)
\(p_T\) resolution at different \(p_T\) values
\(p_T\) resolution
\(\eta\) resolution
\(\phi\) resolution

Results

3 stubs NN

  • Fully connected Neural Network
  • Architecture:
    • Input size: \(3\times 11\)
    • Hidden Layers: \(32, 32, 32, 8\)
    • Output Size: \(3\)
\(p_T\) resolution at different \(p_T\) values
\(p_T\) resolution
\(\eta\) resolution
\(\phi\) resolution

Results

4 stubs NN

  • Fully connected Neural Network
  • Architecture:
    • Input size: \(4\times 11\)
    • Hidden Layers: \(16, 16, 16, 8\)
    • Output Size: \(3\)
\(p_T\) resolution at different \(p_T\) values
\(p_T\) resolution
\(\eta\) resolution
\(\phi\) resolution

Conclusion

Key Takeaways

  • Deep learning is a promising approach to enhancing the performance of the Level-1 trigger.

Backup

Yes it’s fast, but how fast?

L1 trigger

  • Delivering its decision 3.8 μs after the particle collision has occurred
  1. Clock Cycles Required:
    • A single sample takes around 20 clock cycles to be processed.
  2. Operating Frequency:
    • The FPGA pre-processing logic operates at 250 MHz.
    • One clock cycle duration: \(\frac{1}{250 \text{ MHz}} = 4 \text{ ns}\)
  3. Processing Time per Sample:
    • Total time to process one sample: \(20 \text{ cycles} \times 4 \text{ ns/cycle} \approx 80 \text{ ns}\)
  4. Pipeline Architecture:
    • The operation is pipelined, meaning a new sample can enter the process every 4 ns.
    • Full processing of the first sample incurs a latency of ~80 ns.